The function of a DAC is to produce an analog output variable aout (for example current or voltage), which is related to a digital input signal dk (where k ranges from 0 to n−1, and each dk usually is a bit representing a binary state of 0 or 1) by some set of bit weights uk and a reference quantity R. Specifically,
                              α          out                =                  R          ⁢                                    ∑                              k                =                0                                            n                -                1                                      ⁢                                          w                k                            ⁢                              d                k                                                                        (        1        )            
Many codings are known, including binary:
            w      k        =          2              k        -        α              ,            or      ⁢                          ⁢              w        k              =          1      n      Two architectures which implement this function are the voltage-switched resistor DAC and the charge-scaling DAC.
As illustrated in FIG. 1, a voltage-switched resistor DAC includes a collection of accuracy-determining resistors each connected at one end to a single node. The opposite ends of the resistors are then individually and selectively switched between two or more terminals according the binary state of the corresponding bit of the digital input signal. When the resistors are sized by Rk=RT/wk for some chosen value of RT, and the resistors connected to a voltage VR or 0 for dk=1 or 0 respectively, the circuit behaves as a constant resistance
  (            R      T        /                  ∑                  k          =          0                          n          -          1                    ⁢              w        k              )to a voltage in accordance with Equation (1), where R=VR.
An application of a four-element voltage-switched resistor DAC is shown as circuit 100 in FIG. 1. Resistors 102-105 and switches 132-135 comprise the network described above. Operational amplifier 145 and feedback resistor 140 provide a buffered output voltage in accordance with Equation 1, with
  R  =            -              V        R              ⁢                  R        F                    R        T              ⁢                  ∑                  k          =          0                          n          -          1                    ⁢                        w          k                .            
A charge-scaling DAC, an example of which is shown in FIG. 2 includes a collection of accuracy-determining capacitors connected at one end to a single node. The opposite ends of the capacitors are then individually switched between two or more terminals on the basis of a digital input signal. An additional switch is required to define the initial condition of the capacitors by setting the voltage at the node. When the capacitors are sized by Ck=CTwk, the circuit behaves as a constant capacitance
  (            C      T        ⁢                  ∑                  k          =          0                          n          -          1                    ⁢              w        k              )to a voltage in accordance with Equation (1), determined by the initial conditions and the voltages present at the terminals.
An application of a four-element charge-scaling DAC is shown as circuit 200 in FIG. 2. Capacitors 202-205 and switches 232-235 are the network above, with switch 230 providing the initial conditions. Transconductance amplifier 245 and feedback capacitance 240 provide a buffered output at vOUT in accordance with Equation 1. Specifically, if switch 230 was most recently closed with VR=VR0 and dk=ek, then when switch 230 is opened,
      v    out    =                              C          T                ⁢                              ∑                          k              =              0                                      n              -              1                                ⁢                      w            k                                      C        F              ⁢                  (                                            V                              R                ⁢                                                                  ⁢                0                                      ⁢                                          ∑                                  k                  =                  0                                                  n                  -                  1                                            ⁢                                                e                  k                                ⁢                                  w                  k                                                              -                                    V              R                        ⁢                                          ∑                                  k                  =                  0                                                  n                  -                  1                                            ⁢                                                d                  k                                ⁢                                  w                  k                                                                    )            .      The implied subtraction function is useful in constructing successive-approximation ADCs using the DAC network to additionally provide the required sample-and-hold and residue-subtraction functions. A description of a charge-scaling DAC used in a successive-approximation ADC is provided in J. L. McCreary and P. R. Gray, “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques—Part I,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 371-379, December 1975, and incorporated herein by reference.
The two voltage-switched DAC architectures described above have differing performance characteristics. Specifically, the architectures described both include accuracy-determining elements and accuracy-degrading elements. The accuracy-determining elements are those which are intentionally inserted into the DAC and whose values are chosen to give the desired weights and accuracy. In the case of the voltage-switched resistor DAC, this corresponds to the resistors, and in the charge-scaling DAC to the capacitors.
Added to these elements are a number of accuracy-degrading elements and other factors. For the voltage-switched resistor DAC, for example, the on-state resistance of the switches, the parasitic resistance of interconnect wiring, and the non-zero impedance provided by the source of the reference all degrade the accuracy that would be attainable with the resistors alone. For the charge-scaling DAC, parasitic interconnect capacitances degrade the accuracy. Additional degradation occurs due to self-heating effects in the resistors of the voltage-switched resistor DAC and leakage currents of the capacitors of the charge-scaling DAC.
The settling speed of the two approaches depends greatly on the implementation details. The voltage-switched resistor DAC's settling behavior is determined primarily by the parallel impedance of the resistors and the parasitic capacitance of the output. The charge-scaling DAC's behavior, on the other hand, is determined by the parasitic parallel impedance of the switches and interconnect and the total parallel capacitance.
Ignoring the noise of the required references and biases, the noise of the voltage-switched resistor DAC is determined by the value of the parallel resistance, so both speed and noise may be improved by lowering RT, at the cost of exacerbating the impact of the accuracy-degrading factors described above, and drawing additional power.
The charge-scaling DAC's noise, on the other hand, is determined by the √{square root over (kT/CT)} noise sampled at the end of the reset phase, so better noise and accuracy comes at the cost of slower settling and increased power.
The reference current draw of the voltage-switched resistor DAC has a low frequency component which varies non-linearly with the output and thereby degrades the system accuracy. On the other hand, the charge-scaling DAC has high inrush currents when it is switched, also causing an accuracy-degrading disturbance to the system.
Thus, there are drawbacks to both voltage-switched and charge-scaling DAC architectures as described above. It is therefore desirable to produce a new DAC structure which allows less constrained optimization of the performance.